1. Field of the Invention
The present invention relates to a multisense-adaptive reading circuit and reading method.
More specifically the invention relates to a multisense-adaptive reading circuit, associated to a sense element of an interleaved DC-DC converter module and comprising at least a first and second current source connected to a first and second terminal of said module, connected in turn to a first and second resistive element, as well as a tracker of a current information coming from said first and second current source.
The invention also relates to a multisense-self-adaptive reading method.
The invention relates particularly, but not exclusively, to a reading circuit used by the modules of an interleaved DC-DC converter and the following description is made with reference to this field of application for convenience of illustration only.
2. Description of the Related Art
As it is well known, the continuous development of the electric features of processors or CPUs (acronym for the English Computing Processing Unit) for PCs, workstations and servers force producers to look for ever-new solutions to meet the requirements required by central processing units or CPUs. In particular, latest generation CPUs require a high supply voltage precision, equal for example to +/−0.8% in the steady state and +/−3% in the transient state.
Besides these precision requirements, the supply voltages being used fall to 0.8V and load currents rise to 120 A with edges of 100 A/μs, with an efficiency requirements exceeding 80%.
It is thus a matter of using convenient voltage or current controller devices being capable to ensure the required efficiency. Such a device comprises for example an interleaving DC-DC converter, used as an economic and effective solution to meet said requirements and to obtain an output voltage value starting from an input voltage value Vin being equal to 12V+/−1.2V through an ATX bus or equal to 5V+/−0.5V through an ATX bus.
In particular, such a converter topology is obtained by connecting in parallel N Buck-or-step-down-configured DC converters, i.e., by connecting the input and output terminals together. Each DC-DC converter is called module, channel or phase.
The known DC-DC converter interleaving configuration also implies that a convenient clock circuit closes high-side switches comprised in the N modules with a phase displacement corresponding to the switching period T divided by the number N of modules.
By applying the well known voltage control mode to an interleaving configuration such as the one being described, an uncontrolled distribution of the currents in the inductances of the parallel N modules is obtained. It is instead desirable to obtain a predetermined total load current with an egalitarian distribution between the modules, i.e., to obtain that each module carries a current being equal to the output current required divided by N.
To this purpose it is known to use a so-called “current sharing” technique.
Besides the need to use the current sharing technique, the known interleaving-configured DC-DC converter must be able to vary the output voltage value thereof proportionally to the total current required. In other words, by indicating with VID a nominal output voltage value when the DC-DC converter provides a null current value and being I a required output current value, the output voltage value Vout is given by:Vout=VID−I×Rdroopwhere Rdroop is a factor which is programmable outside the DC-DC converter and variable according to the CPUs wherein this DC-DC converter must be used. Thus it is dealt with droop functions or voltage positioning.
Such a DC-DC converter must also control that an anomalous current load does not damage the devices fed thereby. In particular the over current or short circuit conditions into which a load degenerates are conditions which must be traced and remedied by a control system associated to the DC-DC converter protecting the load, i.e., the devices connected to the interleaving DC-DC converter.
All these control and protection functions (i.e., the “voltage positioning”, the “current sharing” and the protection against “Over current” and “Short Circuit” conditions) implies an effective reading and processing system of an analogue information corresponding to a current value of each module.
Known reading systems, in order to meet the Current Sharing and droop function requirements, are designed in order to read or evaluate a current value being delivered by each module towards the output terminal thereof. In particular, a known reading system reads this module current value as a voltage drop across a resistance associated to each module. This resistance can be a module parasitic element (such as a turn-on resistance Rds, on of power switches comprised therein or an inductance resistance DCR) or it can be an element being suitably inserted in the circuit (a reading resistance Rsense arranged in series with the power switches or the inductance).
The first solution is more economical since it exploits elements being already comprised in the module topology, but it provides an inaccurate reading since it is sensitive to the component production variations and to the temperature thereof.
The second solution has the advantage to obtain a very precise and temperature-independent reading, for example realising these supplementary elements with constantan, with the drawback of a higher cost and a conversion efficiency reduction.
FIGS. 1A to 1C show different operating conditions of an interleaved DC-DC converter comprising N modules, comprising in turn a HighSide switch and a LowSide switch realised by means of power transistors. It is assumed that at the output a current I is required, which is equally distributed between the N modules.
In particular, each module 10 comprises a transistor MH serving as a HighSide switch being series-connected to a transistor ML serving as a LowSide switch between a first and second voltage reference, particularly an input voltage Vin and a ground GND. This input voltage Vin is particularly applied to an ATX bus.
The module 10 also comprises the series of an inductor L and an output capacitor Cout being inserted between an intermediate node X between the transistors MH and ML and the ground.
An output voltage value Vout of the module 10 is across the capacitor Cout.
The following cases occur:
1) As shown in FIG. 1A, the reading of a current IA of the module 10 occurs between a drain terminal and a source terminal of the transistor MH, i.e., of the HighSide switch of the module 10.
In that case, the reading is few dissipative since the module current IA flows in the transistor MH, which is a power MOS transistor, only for a time equal to DTs (where Ts is the switching period of the switches MH and ML and D is the duty cycle or the time percentage with respect to Ts wherein the transistor is on). Thus it results that the module 10 dissipates a very reduced power especially for a 5V ATX bus.
Moreover, when the switch or transistor MH closes and the source terminal thereof reaches a voltage value being equal to the input voltage Vin, the reading is damaged because of the noise due to the capacitive and inductive coupling effects.
All this makes the reading very difficult.
In practise, the reading across the transistor MH is used with a conversion from Vin to Vout starting from the ATX bus and thus with a sufficiently large time interval DTs wherein the transistor MH is closed.
2) As shown in FIG. 1B, the reading of a current IB of the module 10 occurs between the drain terminal and the source terminal of the transistor ML, i.e., of the LowSide switch of the module 10.
In this case the transistor ML closes for a time equal to (1−D)Ts (where Ts is always the switching time of the switches MH and ML and D is the duty cycle).
There is thus much more time available, the reading can thus be performed for any ATX bus being used. The reading can eventually be performed even with a reading resistance Rsense arranged in series with the transistor ML.
3) As shown in FIG. 1C, the reading of a current IC of the module 10 occurs across the inductor L.
In that case, the reading performed by using an outer reading resistance would be extremely dissipative. A parasitic resistance DCR of the inductor L is thus be used.
Actually, since a terminal of the inductor L oscillates between a ground voltage value GND and the input voltage value Vin, the reading must be acquired by filtering the current value on that parasitic resistance DCR in order to draw a continuous information and an alternate information repeating the original ripple of the current flowing through the inductor L.
In particular, it is possible to use a filter configuration RC comprising the series of a resistor R1 and of a capacitor C1 connected across the inductor L. Moreover, these supplementary elements R1, C1 must be so sized that it results:R1×C1=L/DCR
It can thus be perceived that parametric variations of these components cannot ensure that the above-cited condition is always meet, damaging in this case the speed and the performances of the so-obtained module.
It is also possible to cancel this drawback by using a reading resistance Rsense arranged in series with the inductor L, as shown in FIG. 1C. In that case, an 5V or 12V ATX bus can be used as an input voltage value Vin.
Obviously, different reading systems correspond to the above-indicated reading conditions. In particular:
1) By reading the voltage signal across the transistor MH it is possible to draw the load current information only during the transistor conduction. It is thus necessary to avoid reading both during the conduction period of the transistor ML and during the conduction of the schottky diode (or of the intrinsic diode of the synchronous MOS transistor) or during the dead time. In order to minimise the noise in reading it is also worth avoiding the turn-on and turn-off instants of the transistor MH whereon the reading is performed and the turn-on and turn-off instants of the power switches of the remaining phases.
It is thus necessary to insert a tracking system of the collected information.
This system is few dissipative, but of very difficult application in the converters being concerned for power supply CPU applications. In fact in these applications the conduction of the transistor MH occurs for a very short time interval given by Vout/Vin×Ts, where Ts is the switching period.
Since the reading system has a lowest latency time being required to acquire the information and to track it, this constrains the application to a lowest switching period.
2) By reading the voltage signal across the transistor ML it is possible to draw the load current information only during the transistor ML conduction, as seen with reference to the reading on the transistor MH. Also in that case it is necessary to track the analogue information represented by the voltage across the sense element Rsense in an instant far from the switchings of the other components; in the remaining time hold the last value acquired from the information, as described in the Italian patent application No. MI2000A002042 filed on Sep. 19, 2000 in the name of the Applicant itself.
3) By reading the voltage signal across the inductor L (i.e., across the filtering capacity C1) on the contrary the information being obtained is always valid and thus it does not require any tracking. It is perceived therefrom that for the noise-freedom the best reading system is composed by a reading resistance arranged in series with the inductor. Unfortunately this system is the most dissipative of all.
The information acquired by the reading system must be used to perform simultaneously four different functions:
Average Current Mode: it allows the output voltage Vout to be regulated ensuring a fast response to load variations. It also allows a correct current sharing between the modules 10 during the transients to be obtained.
Droop function: The current information is used to shift the reference of a feedback loop proportionally to the load.
Average current sharing: By comparing the so-obtained current of each module with the average current value a control signal of a voltage loop of each module is corrected in order to correct the unbalances between the different modules and equalise the current thereof.
Current limit: In order to obtain a precise and fast current limit an instantaneous, and thus not filtered, information on the current is required. In order to limit the highest current deliverable by the module it is necessary to adapt the limiting mechanism to the reading type.
In particular, when reading on the transistor MH and on the inductor L it is sufficient to turn the transistor MH off whenever the detected current thereof exceeds a set threshold. When reading on the transistor ML, which is already in the falling phase of the inductor L current, the mechanism is more complex, as described in the above-cited patent application.
The technical problem underlying the present invention is to provide a reading circuit for interleaved DC-DC converters, having such structural and functional features as to automatically adapt to a component being used as a reading or “sense” resistance, giving the user the greatest latitude to decide how to optimise the controller design and thus overcoming the limits and drawbacks still affecting the reading circuit realised according to the prior art.